Friends who have been doing FPGA for a long time, is there such an experience: an FPGA design project, found in the R&D test phase or the transition to the pilot phase, the FPGA system occasionally has an abnormal phenomenon after power-on operation? In other words, repeated power-on tests sometimes lead to abnormal or functional failures.
This happens, mostly due to improper reset signal in the design.
When we deal with reset problems, many designers usually have the following situations: 1. Use a global asynchronous reset signal 2. Omit the reset signal. The initial value of DFF can use the default value of power-up when the default value can be used. When a special DFF initial value is required, the compiler is told that these DFFs use the iniTIal value after power-up. These practices have their own advantages and are not elaborated here.
Here is a deep-rooted design concept: for the global reset signal, as long as its pulse width is long enough to ensure system reset security. In fact, the TIming Analyzer attached to our ISE analyzes the reset signal, focusing on whether the timing of the system is correct after the reset signal is cancelled.
This is a point we often overlook in design, so it causes the strange phenomenon mentioned at the beginning of the article.
Because in the FPGA chip, the clk signal uses a dedicated clock network, and its skew value is small, but the rst signal in the design has a large fan-out, because it does not use those skew low traces, it is everywhere in the entire chip. The rst signal skew used by DFF is very different. Those weird phenomena are often caused by DFFs with feedback loops in our design. The modules that create these feedback loops are often finite state machines. It is necessary to know whether the function of the finite state machine is normal.
JUMP WELL brand platform image scanner. The use of environmentally friendly fill light, eye protection mode, support a whole day of work effortlessly, imaging technology, megapixels, so that every scan can be easily and quickly, can be widely used in supermarket platforms, catering industry, logistics industry, etc. It can easily deal with the super-large warehousing products. The appearance is simple and beautiful, and the bottom has a non-slip design, so that the scanning instrument is not easily damaged by slipping.
Platform Type Scanner,Supermarket Cashier Scanner,Front Desk Cashier Scanner,Catering Platform Cashier Scanner
Shenzhen Geyi Technology Co., Ltd. , https://www.gy-printer.cn