Xilinx's Spartan-3E Starter Kit development board uploads Intel's 16 MByte (128 Mbit) parallel NOR Flash, FLASH model is 28F128J3, detailed DATA SHEET online can be found for reference. On the EDK hardware we use XILINX's XPS MulTI-CHannel External Memory Controller (XPS MCH EMC) interface IP to connect to FLASH. If we use BSB to build the project, after selecting the Spartan-3E Starter Kit development board, you can directly select FLASH in the following steps, which is convenient. If you are adding IP to an existing IP Catalog, you must also specify the pin connection and PAD position. Refer to Xilinx's UG230: Spartan-3E FPGA Starter Kit Board User Guide, Chapter 11 for specific PAD locations. . In the UCF file of the Project file below the Project column on the left side of the XPS interface, specify the pin, which is a little troublesome. It is recommended to establish the project directly through the BSB by the first method. Please refer to Xilinx Documentation for the use of specific IP cores: XPS MulTI-CHannel External Memory Controller Product SpecificaTIon.pdf.
The XC3S500E FPGA on the Xilinx Spartan-3E Starter Kit development board supports the BPI (Byte Peripheral Interface) configuration mode. To implement BPI mode configuration, first jump the Spartan-3E Starter Kit development board J30. For details, please refer to Table 11-4 on page 89 of the Xilinx Document UG230: Spartan-3E FPGA Starter Kit Board User Guide. Select BPI UP (BPI DOWN) mode, FPGA configuration data should be placed in the low (high) address space of FLASH, here note that 28F128J3 FLASH has &TImes; 8 (data bus width is 8 bits, then the data bus high 8 bits are not used The data is placed in the lower 8 bits of the bus) and ×16 (the data bus width is 16 bits). When configuring, it should work in ×8 mode. After the configuration is completed, we set it to ×16 mode, which is selected by FLASH BYTE# pin. When BYTE# pin is low, it is selected as ×8 working mode, which is high. When the level is selected, the ×16 working mode is selected. The BYTE# pin is connected to the LDC2 (C17) pin of the FPGA. The configuration bitstream file is first converted into an MCS file by the iMPCT tool. The specific steps are: select Prepare a PROM File, press NEXT, select the Generic Parallel PROM and MCS file format, specify the name and save location of the generated file, press NEXT, after pressing NEXT Enter the Select PROM device interface, select the PROM size of 16M and Create BPI-Mode PROM and press NEXT to select the BIT file to be converted. Then we can download it to FLASH through Xilinx's PicoBlaze NOR Flash Programmer(). Of course, we can also use the MicroBlaze processor to write a FLASH project to download the MCS file to FLASH, but it is not as convenient as direct use. Interested friends can also research or modify the PicoBlaze NOR Flash Programmer project, which has PicoBlaze's assembly source.
Introduce the composition of the target code segment after compilation of the MicroBlaze project:
.text: Stores the instruction code.
.rodata: Stores read-only variables.
.data: store global and static variables with initial values
.sdata::Stores small global and static variables with initial values
.sdata2: store small global and static variables with initial values
.bss: store global and static variables without initial values
.sbss: store small global and static variables without initial values
.sbss2: Store small global and static variables with initial values. We are going to execute the program directly on NOR FLASH, so we need to define read-only segments (including .text, .rodata, .sdata2, .sbss2) to the FLASH address space. , define other segments to the BRAM in the FPGA chip.
The following is a practical example to introduce the specific steps:
1. First, follow the steps in the previous section to create an XPS project and application. Add the FLASH to the peripheral selection during the BSP phase. At this time, the system automatically adds the XPS MCH EMC interface IP.
2. We will first put all the segments in the BRAM. After compiling and downloading, we can see that the LED is running.
3. Configuring XPS MCH The EMC interface IP is connected to the MicroBlaze processor with a PLB. There is no MCH channel. The others are default.
4. Click the project name on the left side of the XPS interface, select Generate Linker Script in the right-click pop-up menu, and select the storage space of the segment in the pop-up dialog box. Select the read-only segments .text, .rodata, .sdata2, .sbss2 to FLASH_C_MEM0_BASEADDR. The other segments are selected to ilmb_cntlr_dlmb_ cntlr, and the project is recompiled to produce an executable link file (ELF file).
5. Copy the executable.elf generated in step 4 to the project directory, then select Project → Launch EDK Shell on the XPS interface and enter the following command at the command line:
Mb-objcopy \
--set-section-flags .text=alloc,readonly,code \
--set-section-flags .init=alloc,readonly,code \
--set-section-flags .fini=alloc,readonly,code \
--set-section-flags .text=alloc,readonly,code \
--set-section-flags .rodata=alloc \
--set-section-flags .sdata=contents \
--set-section-flags .sbbs=contents executable.elf volatile.elf
This can store the contents of the BRAM in a volatile.elf file.
Then enter the following command at the command line:
Mb-objcopy –O binary -j .text –j .fini –j .init –j rodata –j sdata2 –j .sbss2 executable.elf flash.bin
This can store the flash.bin file in the FLASH content.
6. Burn the flash.bin file to FLASH. This can be downloaded from the PicoBlaze NOR Flash Programmer project serial port above. You can also use the XPS interface to select Device Configuration → Program Flash Memory to download. Note that XPS is not used to generate BootLoad.
7. Rename the volatile.elf generated in the fifth step to executable.elf to overwrite the executable.elf file generated in step 4.
Then use the XPS interface to select Device Configuration → Updata Bitstream and Device Configuration → Download Bitstream to download the contents of the BRAM and the FPGA configuration data to the FPGA.
Now you can see that the LED is running, but obviously you can see that the speed is much slower, indicating that the program is executed on NOR FLASH. If the speed requirement is not high, it is enough to expand a NOR FLASH to store code and data. Otherwise, we need to expand a piece of RAM, store the code and data in RAM faster, and need a BOOTLAOD project for power-on. Achieve the ability to move code and data from FLASH to RAM.
Finally, if the content of the BRAM and the FPGA configuration data are to be stored on the FLASH for power-up, use BPI to download. Note that the address space where the configuration data is stored and the address space of the application cannot overlap. A simple method is to use BPI. DOWN mode, put the configuration data in the space behind the FLASH, of course, we can also use the paging method to solve.
Relative to SC To SC UPC Duplex,Optical fiber jumpers (also known as optical fiber connectors), that is, optical fiber connectors that are connected to optical modules, are also available in many types, and they cannot be used mutually. The SFP module is connected to the LC fiber optic connector, and the GBIC is connected to the SC fiber optic connector. The following is a detailed description of several commonly used optical fiber connectors in network engineering:
â‘ FC-type fiber jumper: The external strengthening method is a metal sleeve, and the fastening method is a turnbuckle. Generally used on the ODF side (most used on the distribution frame)
â‘¡SC type optical fiber jumper: the connector that connects to the GBIC optical module, its shell is rectangular, and the fastening method is a plug-in latch type, without rotation. (Most used on router switches)
â‘¢ST type optical fiber jumper: commonly used in optical fiber distribution frame, the shell is round, and the fastening method is turnbuckle. (For 10Base-F connection, the connector is usually ST type. Commonly used in optical fiber distribution frame)
â‘£LC-type optical fiber jumper: the connector for connecting the SFP module, which is made by the easy-to-operate modular jack (RJ) latch mechanism. (Router commonly used)
Sc To Sc Upc Duplex,Sc To Sc Upc Simplex,Sc Upc To Sc Apc Simplex,Sc To Sc Apc Duplex
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