At this year's International Solid State Circuits Conference (ISSCC 2016), two automotive system-on-a-chip (SoC)s became the most interesting and innovative wafer technology demonstrations on the digital processor agenda; they were each based on MediaTek. The latest smartphones and PC processors released with AMD contain more cores and adopt more aggressive process technologies.
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The two automotive chips are Renesas design and 16nm FinFET process, one of which is ISO26262 compliant, contains 8 ARM v8 cores, 2 ARM R7 cores and 3 Imagination graphics processing (GPU) cores. The vehicle safety chip; the other is a video processor chip for the car communication entertainment system and driver assistance system application, using six different types of 17 video processors.
“In the past, the technology enabler was a smart phone application processor, but the situation has changed;†Seiji Mochizuki, a senior engineer at Renesas who was involved in the design of the video SoC, said in an interview that it is based on the car’s communication and entertainment system and driving. Note the requirements of the system: "The automotive SoC will require much higher performance than the smart phone processor, and future automotive processors must be developed with the most advanced technology."
Another Renesas engineer, Chikafumi Takahashi, who is responsible for vehicle safety SoC development, added: "This is a demand from the market because we need to process a lot of information.
Renesas developed a vehicle safety processor using 16nm process technology
David Kanter, a frequent visitor and microprocessor analyst at ISSCC, agrees that the power limit of a car is not as much as that of a mobile phone, and that the demand for chips is growing rapidly, especially for autonomous vehicles that will be available in the next decade: The slowdown in the mobile phone market means that everyone is looking for the next big business opportunity. Obviously, the data center field is already Intel's world, but there are still many opportunities in the automotive field that can be differentiated by vendors such as Nvidia. â€
Kanter pointed out that the car is also a mature application environment that can integrate and virtualize many functions in a single chip, and can use the method of individual design in safety-critical functions as demonstrated by Renesas. Renesas' car video processors are now sampling, but security chips are still being evaluated.
High-resolution video decoding with 12-channel Renesas processor consumes only 197mW
MediaTek smart phone application processor contains 10 cores
The car processor has not completely compared the mobile phone processor. Currently, only a few chips on the market use the 14/16nm FinFET process; mainly Apple (Apple), Samsung (Samsung) smart phone application processor, and Qualcomm's Snapdragon chip.
After the latest smart phone processor released by MediaTek in ISSCC, it also integrated 8 Cortex-A53, 2 A57 cores, as well as GPU, data machine and multimedia subsystem. The chip uses a 20nm process to divide the processor core into three clusters; the mid-range 2GHz A53 core cluster occupies a unique position, providing 40% higher performance than the lower-order 1.4G A53 core cluster, and higher than 2.5 GHz. The A72 core cluster consumes 40% less power.
Uming Ko, vice president of technology at MediaTek, said that because of the small size of the chip, there are no restrictions on how many cores can be integrated in the mobile phone processor: "If you draw a straight line between ultra low power and high performance, there is enough The performance points allow you to continue to find the benefits of adding enough cores."
MediaTek's 20nm process application processor has begun shipping
AMD engineers demonstrated a clever way to increase the performance of their PC processor Carrizo by 15% - simply by providing more aggressive power management techniques into the 28nm process design. The Bristol Ridge platform is designed to take advantage of power management schemes to overcome performance limitations associated with heat, voltage, and current.
16nm design challenge
In addition, I also asked Renesas engineers about the design experience of the 16nm node. The processor design using this process needs to overcome the challenges of multi-patterning and FinFET. The chip architecture needs to be changed to some extent; There are other opinions.
Takahashi said: "The 16nm node has many challenges and difficulties... The work number is a problem, sometimes reliability is also a problem;" He pointed out that the 16nm chip memory cell is very small, and the memory lines are very short, so More susceptible to software errors. â€
Takahasi also said that the foundry will provide 16nm interconnects, but lacks support for advanced features, such as Renesas' built-in quality-of-service controls on its own chips. To simplify 16nm design and verification, a higher-order design language such as System C is required.
In addition, Mochizuki pointed out that the 16nm chip uses a relatively high frequency clock and it is difficult to maintain low power consumption; he said that the 16nm node: "There is less flexibility compared to the previous generations of processes... In order to reduce power consumption, we may need Change the design pattern."
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